library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pipemem is
	generic
	(
		ADDRESS_WIDTH : natural := 	32;	
		DATA_WIDTH	: natural  :=	32
	);


	port
	(
		-- Input ports
		re : in std_logic;
		we : in std_logic;
		a : in std_logic_vector(DATA_WIDTH-1 downto 0);
		di : in std_logic_vector(DATA_WIDTH-1 downto 0);
		clk : in std_logic; -- CPU Clock
		memclk : in std_logic; -- Memory Clock
		-- Output ports
		dcacheok : out std_logic;
		-- mmo
		dataout : out std_logic_vector(DATA_WIDTH-1 downto 0)
	);
end pipemem;

architecture rtl_pipemem of pipemem is
component lpm_ram_dq0
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
end component;
component cache
	port
	(
		-- Input ports
		clk	: in std_logic;
		mclk : in std_logic;
		address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
		wen : in std_logic;
		ren : in std_logic;
		data_f_cpu : in std_logic_vector(DATA_WIDTH-1 downto 0);
		data_f_mem : in std_logic_vector(DATA_WIDTH-1 downto 0);

		-- Output ports
		tmp_m1 : out std_logic;
		tmp_m2 : out std_logic;
		state_out : out integer;
		dcacheok_t_cpu : out std_logic;	
		data_t_cpu : out std_logic_vector(DATA_WIDTH-1 downto 0);
		addr_t_mem : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
		data_t_mem : out std_logic_vector(DATA_WIDTH-1 downto 0);
		write_t_mem : out std_logic
	);
end component;
signal data_f_mem,data_t_mem : std_logic_vector(DATA_WIDTH-1 downto 0);
signal addr_t_mem : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal write_t_mem : std_logic;
begin
	cache_L1: cache port map(
		clk => clk,
		mclk => memclk,
		address => a,
		wen => we,
		ren => re,
		data_f_cpu => di,
		data_f_mem => data_f_mem,
		
		dcacheok_t_cpu => dcacheok,
		data_t_cpu => dataout,
		addr_t_mem => addr_t_mem,
		data_t_mem => data_t_mem,
		write_t_mem => write_t_mem
	);
	datamem: lpm_ram_dq0 port map(
		address => addr_t_mem(6 downto 2),
		clock => memclk,
		data => data_t_mem,
		wren => write_t_mem,
		q => data_f_mem
	);
end rtl_pipemem;
